RISC-V Multicore Processor

Problem Statement

Students need practical exposure to multicore processor architecture, pipelining, FPU and FPGA prototyping.

Objectives

• - Design multicore RISC-V in Verilog
• - Integrate F-extension floating point support
• - Implement SIMD-style matrix ops
• - Prototype with UART communication

Methodology

The project follows a structured implementation approach that includes ISA and architecture study, Datapath, pipeline and hazard handling design, Multicore dispatcher and shared memory protocol, and Simulation and FPGA validation. These steps are executed iteratively to validate assumptions, improve performance, and ensure reliable delivery of the final solution.

Expected Outcome

By the end of this project, the team is expected to deliver Functional multicore processor prototype, Verified FPU and matrix acceleration, and FPGA demonstration with UART. Together, these outcomes reflect both technical feasibility and practical value for demos, evaluation, and future scaling.

Future Scope

• - Cache hierarchy enhancements
• - Compiler support for high-level toolchains
• - Benchmarking against mainstream architectures

Components and Budget